1. Field of the Invention
The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input.
2. Description of the Related Art
Recently, various data communications including packet communications on networks typified by the Internet and communications of image data obtained by digital cameras have been used widely. Such communications employ buffer devices to store transmitted data temporarily to retransmit data in case of error during data transmission.
For example, packet communications compliant with the PCI Express standard can send and receive data packets of arbitrary data length. Buffer devices used in the packet communications can temporarily store multiple data packets of arbitrary data length.
FIG. 4 is a schematic block diagram showing an embodiment of a conventional buffer device.
The buffer device shown in FIG. 4 is used for packet communications compliant with the PCI Express standard. It receives input of data packets of arbitrary data length, stores the data packets, and outputs the stored data packets in order of input. The buffer device 50 is equipped with a data buffer 51, write pointer 52, read pointer 53, data input control circuit 54, write pointer control circuit 55, data output control circuit 56, and read pointer control circuit 57.
The data buffer 51 of the buffer device 50 shown in FIG. 4 has data areas which store data packets. The size of the data areas is expressed as a power of 2.
The write pointer 52 memorizes a write position which is located in the data areas of the data buffer 51 and in which a data packet is to be stored next.
The read pointer 53 memorizes a read position which is located in the data areas of the data buffer 51 and from which a data packet is to be read next.
When inputting a data packet in the data areas of the data buffer 51, the data length of the data packet to be inputted is compared with the size of available data areas. Since the size of the data areas of the data buffer 51 is expressed as a power of 2 as described above, the size of available data areas is given in binary format by equation (1) below.(Size of available data areas)=(Size of data areas)−(Write pointer)+(Read pointer)  (1)
The data input control circuit 54 receives input of a data packet, determines the size of available data areas using equation (1) and stores the inputted data packet in the write position located in the data areas of the data buffer 51 and memorized by the write pointer 52 if the size of available data areas turns out to be larger than the data length of the data packet.
The write pointer control circuit 55 changes the write position memorized by the write pointer 52 by the length equal to the data length of the newly stored data packet each time a data packet is stored by the data input control circuit 54.
The data output control circuit 56 reads and outputs data packets stored in the data areas of the data buffer 51, from the read positions located in the data areas and memorized by the read pointer 53, in order of input.
After the data packets are outputted by the data output control circuit 56, the read pointer control circuit 57 receives a notice (hereinafter referred to as an ACK (Acknowledgment) notice) from the external device which has received the data packets, stating that the data packets have been received successfully and requesting that areas be freed for a specified number of data items. Consequently, the read pointer control circuit 57 changes the read position memorized by the read pointer 53 by the length equal to the data length of the data packets and thereby frees the data areas occupied by the data packets.
Each data packet of arbitrary data length contains data length information which represents the data length, in its header section.
Upon receiving the ACK notice, the read pointer control circuit 57 of the conventional buffer device 50 shown in FIG. 4 reads the data length information from the header section of a specified data packet and changes the read position by the length equal to the data length indicated by the data length information read out. Thus, the conventional buffer device 50 has a problem in that data length is read each time a data packet is unloaded from a data area of the data buffer 51, adding to processing time.
In packet communications compliant with the PCI Express standard, it is permissible to send a notice for a collection of multiple data packets. The read pointer control circuit 57 reads the data length information from the header section of the foremost data packet in the data buffer 51 among the multiple data packets specified in the notice and then determines the head position of the next data packet based on the data length represented by the data length information. Then, the read pointer control circuit 57 reads the data length information about from the determined head position to the next data packet and repeats this process. This further increases the processing time required to unload data packets from data areas of the data buffer 51. This may cause problems of reduced communications speed.